Course Title and Code
VLSI Architectures for Signal Processing and Machine Learning (EE5516)
Programme
B.Tech/MS/M.Tech/PhD
Course Credit
2-0-2-3 (Lecture-Tutorial-Practical-Total Credits)
Course Category
PME
Prerequisite
Digital Systems, Signals and Systems (required); MATLAB/Python Programming, Digital design using Verilog HDL (Desired)
Consent of Teacher
Yes
Course Description
This course introduces the design and implementation of signal processing and machine learning algorithms on resource-constrained systems. The course covers formal techniques, high-level transforms to map algorithms onto hardware, the Least Mean Squared (LMS) algorithm, and machine learning architectures. The course includes hands-on experiments using MATLAB/Python, Verilog, and FPGA implementations. Emphasis will be on system-building, algorithmic reformulations, LMS learning rate analysis, and case studies of algorithm-to-architecture mappings.
Course Content
| S/N | Topic | Lecture (hours) | Lab (hours) |
|---|---|---|---|
| 1 | Fundamentals: Motivation and scope of the course; terminology, applications and platforms, use of block diagrams, signal flow graphs, data-flow graphs, dependence graphs for representing signal processing algorithms | 4 | 0 |
| 2 | High level transformations: Iteration bound, critical path, pipelining and retiming of data-flow graphs; unfolding and folding transformation of dataflow graphs, systolic array architectures, distributed arithmetic, implementation of the transformed DFGs | 9 | 8 |
| 3 | Algorithm to Architecture Mapping Case studies: Performance-complexity trade-offs while mapping an algorithm onto architecture, Case studies of GCD, CORDIC, FFT, Matrix Inversion algorithms and their fixed-point implementations | 5 | 10 |
| 4 | LMS Learning Algorithm: Connection to stochastic gradient descent (SGD) algorithm; applications for time-series data; finite precision effects; case studies of CMOS prototypes of LMS and its variants | 4 | 5 |
| 5 | Hardware Architectures for Machine Learning: Architectural approaches for implementing DNN with reduced precision, model size compression, pruning, and compact network architectures | 6 | 5 |
Learning Outcomes
- Understand the design methodologies for realization of dedicated VLSI architectures for signal processing and machine learning applications
- Understand the area-power-speed trade-offs for different applications
- Familiar with the intrinsic error tolerance of machine learning algorithms and approximate computing
- FPGA implementation of given complex algorithms according to specifications
Teaching Methodology
Classroom lectures and MATLAB/Verilog programming in Lab
Assessment Methods
Written examination, Continuous lab assessment
Text Books
- K.K. Parhi, VLSI Digital Signal Processing Systems: Design and implementation, John Wiley, 1999. ISBN: 978-8-126-51098-6
- U. Meyer-Baese, Digital Signal Processing with Field Programmable Gate Arrays, 4th Ed. Springer, 2014. ISBN 978-3-540-72613-5
References
- V. Sze, "Designing Hardware for Machine Learning," IEEE Solid-State Circuits Magazine, vol. 9, no. 4, pp. 46-54, Fall 2017.
- N. R. Shanbhag, N. Verma, Y. Kim, A. D. Patil, and L. R. Varshney, "Shannon-Inspired Statistical Computing for the Nanoscale Era," Proceedings of the IEEE, vol. 107, no. 1, pp. 90-107, Jan. 2019.
- V. Sze, Y. Chen, T. Yang, and J. S. Emer, "Efficient Processing of Deep Neural Networks: A Tutorial and Survey," Proceedings of the IEEE, vol. 105, no. 12, pp. 2295-2329, Dec. 2017.