Course Title and Code
Principles of SOC Functional Verification (EE5530)
Course Category
Elective
Course Credit
3-0-0-3 (Lecture-Tutorial-Practical-Total Credits)
Target Programme
PG
Target Discipline
M.Tech SOCD, B.Tech (EE)
Prerequisite
Digital System Design, Verilog, Object oriented programming concepts
Course Content
| S/N | Topic | Lecture (hours) |
|---|---|---|
| 1 | Introduction to Functional Verification–Concepts, Challenges, Simulators, Verification Approaches: black box, white box and grey box verification, Phases of verification block level, cluster level, SOC full chip level | 4 |
| 2 | Verification Methodologies: Testing strategy, Directed and random Testing, Test Cases Vs Test Benches, Verification Components (Drivers, Checkers, Monitors, Scoreboards etc) | 8 |
| 3 | System Verilog Paradigm: Limitations of Verilog for verification, Hardware Verification Languages, Object oriented programming for SOC Verification, Process and inter process communication, verification IPs and reuse | 8 |
| 4 | Measuring the quality of verification: Code coverage, Functional coverage, Coverage Driven Verification, Assertion based verification, Coverage Analysis, regressions, debug and best practices | 8 |
| 5 | System Verilog Universal Verification Methodology (UVM) components and practices | 6 |
| 6 | Architecting Test benches: Building actual test benches based on System Verilog from grounds up | 8 |
Course Objectives
The objective of this course is to teach students everything about pre-silicon functional verification of VLSI RTL designs. Emphasis of the course is on frontend design & verification methodologies and on their practical applications. The course contents have been designed keeping in view the emerging trends in needs for skilled manpower in the ASIC/SOC industry.
Learning Outcomes
- Thorough working knowledge in writing test benches
- Proficiency in industry standards and methodologies for functional verification of ASIC/SOC designs
Text Books
- ASIC/SoC Functional Design Verification - Ashok B Mehta, Springer 2018, ISBN 978-3-319-59417-0
- SystemVerilog for Verification – Chris Spear, Springer- 2008, ISBN 978-0-387-76529-7
- SystemVerilog Assertions Handbook: for Formal and Dynamic Verification – Ben Cohen, Srinivasan Venkataramanan, Ajeetha Kumari, Createspace Independent Pub; 4th edition, 2015, ISBN-978-1518681448
Reference Books
- Writing Testbenches using SystemVerilog – Janick Bergeron, Springer, 2013, ISBN: 9780387292212