Course Title and Code

Digital Systems (EE2070)

Programme

UG Core

Course Credit

3-0-2-4 (Lecture-Tutorial-Practical-Total Credits)

Course Category

Core

Target Discipline

EE

Prerequisite

Nil

Course Content

S/N Topic Lecture (hours) Practical (hours)
1 Introduction to Digital systems and Boolean Algebra: Binary, octal and hexadecimal number systems; Basic logic operation and logic gates; truth table; basic postulates and fundamental theorems of Boolean Algebra; Canonical (SOP and POS) forms; Logic minimization and implementation: Minterm and Maxterms; Karnaugh maps; incompletely specified functions; NAND and NOR implementations; Switch level representation using transistors using CMOS 9 0
2 Combinational Logic: Decoder, encoders, multiplexers, demultiplexers and their applications; Arithmetic circuits; Representation of signed numbers; Adders -- ripple carry, carry look ahead, BCD adders 11 6
3 Sequential Logic: Latches and flip flops D latch, D flip-flop, Setup and hold parameters; Timing analysis; Registers and counters; Shift register; Synchronous counter design using D and JK flip-flops, State Machine Design: Definition of state machines; State machine as a sequential controller; Moore and Mealy state machines; Derivation of state graph and tables; Sequence detector; Design state machine using ASM charts; 12 3
4 Memory and Programmable Logic Devices: Read Only Memories FPGAs; Hardware description language: Modeling combinational and sequential circuits using Verilog. 10 12
Total 42 21

Learning Outcomes

  • Understand digital system abstractions such as digital representations of information, digital logic, Boolean algebra, state elements, and finite state machine.
  • Design, build and test digital logic for systems of moderate complexity using common digital components, schematic diagrams, and hardware description language.

List of Experiments

  • Basic AND, OR and Inverter gates and a parity generator on a bread board.
  • Half adder and full adder circuits on a bread board.
  • 4-bit binary counter design using flip flops on a bread board.
  • 4-bit adder design using Verilog hierarchical design, test bench, simulation and FPGA implementation.
  • Traffic light controller design using Verilog hierarchical design, test bench, simulation and FPGA implementation.
  • Accumulator circuit design in Verilog hierarchical design, test bench, simulation and FPGA implementation.
  • Fibonacci series generation on an FPGA using two adders and a register.

Text Books

  • Digital Design With an Introduction to the Verilog HDL, VHDL, and SystemVerilog, Pearson Education; Sixth edition, 2018 ISBN 978-9353062019

Response to Reviewers Comments

Reviewer 1:

  • Agreed that Q-M (Quine-McCluskey) technique is quite inefficient in time and space. However, you may keep it as a programming assignment. Is ESPRESSO logic heuristic minimizer taught in some CAD course? Teaching it in Digital Circuits course would be quite time-consuming.
  • Better to teach students to do (synchronous) sequential circuit design using JK FFs as that would lead to more minimization (compared to DFF) and perhaps keep a JK FF based experiment in the lab.
  • You may include TTL logic while teaching gates and combinational logic modules.

Response:

  • Thanks for the feedback. Teaching or programming assignment in ESPRESSO for logic minimization is beyond the scope of the basic digital systems course. It makes more sense in the advanced courses like VLSI CAD.
  • Agree with the reviewer. Included it in the syllabus.
  • Since CMOS is already part of the syllabus and it is the main technology for digital design for the last 30 years, teaching TTL may not add much value.

Reviewer 2:

  • Overall I like the changes (for example, dropping Quine-McCluskey and TTL are long overdue. A couple of suggestions (I don't know the exact plans for the course so these may or may not fit in with your plans):
  • I agree with your justification that SR latches etc are never used in practice. The only reason they may still be worth briefly reviewing is because they are very simple in structure, and can illustrate the idea of bistable feedback etc more easily for students who are not yet familiar with CMOS inverters and memory structures. Of course, this means I am only looking at them from the point of view of explaining the core idea, not using them much thereafter.
  • One thing I feel is important is to try and give more importance to timing analysis - possible even look at lab experiments that can illustrate why timing is important, or how you decide at what speed systems can work. You do have timing analysis mentioned in the list, but I am not able to gauge how much importance is given to this part.
  • Do you have a separate course on computer organization that is a core? In our case, we removed it as a core requirement, but my suggestion at the time was that the basic ideas of programmability (FSM + memory holding instructions) could be brought in to the digital systems course itself. I am not sure how exactly we are doing it here, but it might be worth exploring.
  • For the FPGA lab - while a 4-bit adder may be OK, would it be possible to go for a more complex design - something like a sequential multiplier? That brings in concepts from both combinational and sequential design, as well as showing how the HDL can be used effectively.

Response:

  • Thanks for the feedback.
  • Sure. We will touch upon the bistable feedback during the explanation of latch and flip-flop.
  • Agreed. We will emphasize more on timing analysis while explaining the D-flip flops.
  • Yes. We do have a core course on microprocessors and interfacing.
  • We do have more complex experiments in sequential design like traffic light controller and Fibonacci series generator.